29F0408
32 Megabit (4M x 8-Bit)
Flash Memory
Logic Diagram
Memory
F
EATURES
:
• Single 5.0 V supply
• Excellent Single Event Effect
· - SEL
TH
: > 60 MeV/mg/cm
2
· - SEU
TH
: = 37 MeV/mg/cm
2
- SEU saturated cross section: 2E-6 cm
2
/bit
• Organization:
- Memory cell array: (4M + 128k) bit x 8bit
- Data register: (512 + 16) bit x 8bit
• Automatic program and erase
- Page program: (512 + 16) Byte
- Block erase: (8K + 256) Byte
- Status register
• 528-Byte page read operation
- Random access: 10 µ s (max)
- Serial page access: 50 ns (min)
• Fast write cycle time
- Program time: 250 µ s (typ)
- Block erase time: 2 ms (typ)
• Command/address/data multiplexed I/O port
• Hardware data protection
- Program/erase lockout during power transitions
• Reliable CMOS floating-gate technology
- Endurance: 1,000,000 program/erase cycles
- Data retention: 10 years
• Command register operation
• 44 pin flat package
D
ESCRIPTION
:
Maxwell Technologies’ 29F0408 high-performance flash mem-
ory. The 29F0408 is a 4M (4,194,304) x 8-bit NAND Flash
Memory with a spare 128K (131,072) x 8-bit. A program oper-
ation programs the 528-byte page in 250 µ s and an erase
operation can be performed in 2 ms on an 8K-byte block. Data
within a page can be read out at 50 ns cycle time per byte.
The on-chip write controller automates all program and erase
functions, including pulse repetition, where required, and inter-
nal verify and margining of data. Even write-intensive systems
can take advantage of the 29F0408’s extended reliability of
1,000,000 program/erase cycles by providing either ECC
(Error Correction Code) or real time mapping-out algorithm.
These algorithms have been implemented in many mass stor-
age applications. The spare 16 bytes of a page combined with
the other 512 bytes can be utilized by system-level ECC. The
29F0408 is an optimum solution for large non-volatile storage
applications such as solid state storage, digital voice recorder,
digital still camera and other portable applications requiring
nonvolatility.
Maxwell Technologies' patented R
AD
-P
AK
® packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. Capable of surviving in space environments, the
29F0408 is ideal for satellite, spacecraft, and space probe
missions. It is available with packaging and screening up to
Class S.
11.08.02 Rev 2
All data sheets are subject to change without notice
1
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
©2002 Maxwell Technologies
All rights reserved.
32 Megabit (4M x 8-Bit) Flash Memory
29F0408
T
ABLE
1. P
INOUT
D
ESCRIPTION
P
IN
2
S
YMBOL
Command Latch
Enable (CLE)
D
ESCRIPTION
The CLE input controls the path activation for commands sent to the command register.
When active high, commands are latched into the command register through the I/O ports
on the rising edge of the WE signal.
3
Address Latch Enable The ALE input controls the path activation for address and input data to the internal
(ALE)
address/data register. Addresses are latched on the rising edge or WE with ALE high, and
input data is latched when ALE is low.
Chip Enable (CE)
The CE input is the device selection control. When CE goes high during a read operation,
the device is returned to standby mode. However, when the device is in the busy state dur-
ing program or erase, CE high is ignored, and does not return the device to standby mode.
The WE input controls writes to the I/O port. Commands, address and data are latched on
the rising edge of the WE pulse.
The RE inputs is the serial data-out control, and when active drives the data onto the I/O
bus. Data is valid t
REA
after the falling edge of RE which also increments the internal column
address counter by one.
The SE input controls the spare area selection when SE is high, the device is deselected
the spare area during Read1, Sequential data input and page Program.
43
4
42
Write Enable (WE)
Read Enable (RE)
40
18-21,
24-27
5
41
Spare Area Enable
(SE)
I/O Port: I/O0 ~ I/O7 The I/O pins are used to input command, address and data, and to output data during read
operations. The I/O pins float to High-Z when the chip is deselected or when the outputs are
disabled.
Write Protect (WP)
Read/Busy (R/B)
The WP pin provides inadvertent write/erase protection during power transitions. The inter-
nal high voltage generator is reset when the WP pin is active low.
The R/B output indicates the status of the device operation. When low, it indicates that a
program, erase or random read operation is in process and returns to high state upon com-
pletion. It is an open drain output and does not float to High-Z condition when the chip is
deselected or when outputs are disabled.
Not Connected
Ground
Supply Voltage
Output Buffer Voltage
6-17, 28-39
1, 22
44
23
NC
V
SS
V
CC
V
CC
Q
11.08.02 Rev 2
All data sheets are subject to change without notice
2
©2002 Maxwell Technologies
All rights reserved.
32 Megabit (4M x 8-Bit) Flash Memory
T
ABLE
2. 29F0408 A
BSOLUTE
M
AXIMUM
R
ATINGS 1,2
P
ARAMETER
Voltage on any pin relative to V
SS
Operating Temperature
Storage temperature
Short circuit output current
S
YMBOL
V
IN
T
BIAS
T
STG
I
OS
M
IN
-0.6
-40
-65
--
29F0408
M
AX
7.0
125
150
5
U
NIT
V
°
C
°
C
mA
1. Minimum DC voltage is -0.3 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods < 30 ns.
Maximum DC voltage on input/output pins is V
CC
+ 0.3 V which, during transitions, may overshoot to V
CC
+ 2.0 V for periods <
20 ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings
conditions for extended periods may affect reliability.
T
ABLE
3. 29F0408 R
ECOMMENDED
O
PERATING
C
ONDITIONS
(V
OLTAGE REFERENCE TO
GND, T
A
= -40
TO
125
°
C)
P
ARAMETER
Supply voltage
Supply voltage
Input High Voltage
Input Low Voltage
S
YMBOL
V
CC
V
SS
V
IH
V
IL
M
IN
4.5
0
2.4
-0.3
T
YP
5.0
0
--
--
M
AX
5.5
0
V
CC
±0.5
0.8
U
NIT
V
V
V
V
T
ABLE
4. D
ELTA
L
IMITS
P
ARAMTER
I
CC
1
I
SB
1
I
SB
2
C
ONDITION
±10%
±10%
±10%
T
ABLE
5. 29F0408 AC T
EST
C
ONDITION
(V
CC
= 5 V ± 10%, T
A
= -40
TO
125
°
C,
UNLESS OTHERWISE NOTED
)
P
ARAMETER
Input pulse levels
Input rise times
Input and output timing levels
M
IN
0.4
--
0.8
M
AX
2.6
5.0
2.0
U
NIT
V
ns
V
11.08.02 Rev 2
All data sheets are subject to change without notice
3
©2002 Maxwell Technologies
All rights reserved.
32 Megabit (4M x 8-Bit) Flash Memory
T
ABLE
6. 29F0408 DC
AND
O
PERATING
C
HARACTERISTICS
(V
CC
= 5 V ± 10%, T
A
= -40
TO
125
°
C,
UNLESS OTHERWISE NOTED
)
P
ARAMETER
Operating current
Sequential
read
Program
Erase
Stand-by-current (TTL)
Stand-by current (CMOS)
Input leakage current
Output leakage current
Input high voltage, all inputs
Input low voltage, all inputs
Output high voltage level
Output low voltage level
Outuput low current (R/B)
S
YMBOL
I
CC1
I
CC2
I
CC3
I
SB1
I
SB2
I
LI
I
LO
V
IH
V
IL
V
OH
V
OL
I
OL
(R/B)
I
OH
= -400 µ A
I
OL
= 2.1 mA
V
OL
= 0.4 V
CE = V
IH
, WP = SE = 0V/V
CC
CE = V
CC
- 0.2, WP = SE =
0V/V
CC
V
IN
= 0 to 5.5 V
V
OUT
= 0 to 5.5 V
T
EST
C
ONDITIONS
t
CYCLE
= 50 ns
CE = V
IL
,
I
OUT
= 0 mA
S
UBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
M
IN
--
--
--
--
--
-10
-10
2.0
--
2.4
--
8
T
YP
15
15
25
--
10
--
--
--
--
--
--
10
29F0408
M
AX
30
30
40
1
100
10
10
--
0.8
--
0.4
--
U
NIT
mA
mA
uA
uA
uA
V
V
V
V
mA
T
ABLE
7. 29F0408 C
APACITANCE 1
P
ARAMETER
Input/Output capacitance
Input capacitance
1. Capacitance Guarenteed by design.
S
YMBOL
C
I/O
C
IN
T
EST
C
ONDITION
V
IL
= 0V
V
IN
= 0V
--
--
10
10
pF
pF
M
IN
M
AX
U
NIT
T
ABLE
8. 29F0408 M
ODE
S
ELECTION
CLE
H
L
H
L
L
ALE
L
H
L
H
L
CE
L
L
L
L
L
WE
RE
H
H
H
H
H
SE
X
X
X
X
L/H
1
WP
X
X
H
H
H
Data Input
Write Mode
Read Mode
M
ODE
Command Input
Address Input (3
Clock)
Command Input
Address Input (3
Clock)
11.08.02 Rev 2
All data sheets are subject to change without notice
4
©2002 Maxwell Technologies
All rights reserved.
32 Megabit (4M x 8-Bit) Flash Memory
T
ABLE
8. 29F0408 M
ODE
S
ELECTION
CLE
L
L
X
X
X
X
ALE
L
L
X
X
X
2
X
CE
L
L
X
X
X
H
WE
H
H
X
X
X
X
H
X
X
X
X
RE
SE
L/H
1
L/H
1
L/H
1
X
X
0V/V
CC3
WP
X
X
H
H
L
29F0408
M
ODE
Sequential Read & Data Output
During Read (Busy)
During Program (Busy)
During Erase (Busy)
Write Protect
0V/V
CC3
Stand-by
1. When SE is high, spare area is deselected.
2. X can be V
IL
or V
IH
.
3. WP should be biased to CMOS high or CMOS low for standby.
T
ABLE
9. 29F0408 P
ROGRAM
/E
RASE
C
HARACTERISTICS
(V
CC
= 5 V ± 10%, T
A
=-40
TO
+125C,
UNLESS OTHERWISE NOTED
)
P
ARAMETER
Program time
Number of partial program cycles in the same page
Block erase time
S
YMBOL
t
PROG
N
OP
t
BERS
M
IN
--
--
--
T
YP
0.25
--
2
M
AX
1.5
10
10
U
NIT
ms
cycles
ms
11.08.02 Rev 2
All data sheets are subject to change without notice
5
©2002 Maxwell Technologies
All rights reserved.
